1. Field of the Disclosure
The present disclosure generally relates to duty cycle corrector (DCC) circuits and, more particularly, to a DCC initialization scheme for a reduced-frequency, 50% DCC.
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other semiconductor memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. Delay-locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving a microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident (or “locked”) with the rising edge of a second clock signal (e.g., the memory internal clock). The second clock signal may be supplied directly or through a duty cycle corrector (DCC) to various circuit components in the electronic device. In a memory device, for example, a 50% DCC circuit may be employed so as to more proportionately spread out data transfer windows, especially when data transfer takes place on both the rising and falling edges of the memory's clock. In case when the memory's clock (e.g., clock output from a DLL (not shown)) has 25% duty cycle, the data transfer window at the rising edge of the clock may be shorter than the window at the falling edge of the clock because of a disproportionate gap between the successive rising and falling edges of the clock. In the event that data transfers are performed with a 50% duty cycle clock, such imbalance may be avoided by having one data transfer window occurring at the rising edge of the 50% duty cycle clock and the second data transfer window occurring at the second rising edge in the same clock cycle of the 50% duty cycle clock.
FIG. 1 depicts a simplified block diagram of a prior art duty cycle corrector (DCC) circuit 10 that may be used in an electronic device (e.g., a memory device) to provide clocks of various phases (signals 19, 20, and 22 in FIG. 1) from an input clock signal 18. More specifically, the DCC circuit 10 may be used to obtain a clock that is exactly 180° out of phase with the input clock 18. A 50% duty cycle clock may then be obtained using such 180° out of phase clock (e.g., the output clock 22 in FIG. 1) as is known in the art. The DCC circuit 10 may be a phase generator configured to generate clocks of various phases. The phase generator 10 may include a pair of series-connected delay lines 12, 14, and a phase detector 16 forming a feedback loop. The input clock (Clock In) signal 18 may be received from a DLL (not shown in FIG. 1, but shown in FIG. 2 and discussed later hereinbelow) and supplied as an input to the first delay line 12 and also as an input to the phase detector 16. One of the outputs of the circuit 10 may be obtained directly from the Clock In signal 18 as a first output clock or Clock Out 0° signal 19. It is evident from FIG. 1 that there is no phase difference (0° of phase difference) between the input clock 18 and the first output clock 19. The second output of the phase generator 10 may be obtained from the output of the first delay line 12 as indicated by the Clock Out 180° signal 22 in FIG. 1. As the name for this second output suggests, the phase difference between the input clock 18 and the Clock Out 180° signal 22 is 180°. Whereas a third output of the phase generator 10 may be obtained at the output of the second delay line 14. This third output, the Clock Out 360° signal 20 in FIG. 1, has a 360° phase difference (i.e., delayed by one full clock cycle) from the input clock 18.
It is seen from FIG. 1 that the output 20 of the second delay line 14 is fed back as the second input to the phase detector 16, which, as is known in the art, compares the phase difference between its two inputs—the Clock In signal 18, and the Clock Out 360° signal 20—and generates a control signal 24 (which is supplied to both the delay lines 12, 14) to control the delays imparted by the delay lines 12, 14 so as to ensure that the loop delay (i.e., the delay between the input signal (Clock In 18) and the feedback signal (Clock Out 360° signal 20)) is exactly one clock cycle (1*tCK, where tCK is the input clock period). The two delay lines 12, 14 have the same control bits and, therefore, they impart same delay to their respective input clocks in response to the control signal 24. Because these two, matched delay lines divide the input clock 18 exactly into two portions, the “midpoint” clock (i.e., the output of the first delay line 12) is always 180° out of phase with the input clock 18 regardless of the input clock period or PVT (process, voltage, and temperature) variations. Thus, a 180° phase clock (the output signal 22 in FIG. 1) may be created using the topology of the phase generator 10. This topology may be expanded, as is known in the art, to arbitrary, multiphase clock generators (e.g., quadrature phase clock, etc.).
FIG. 2 shows a prior art circuit configuration 25 illustrating how a 50% DCC unit 26 is used in an electronic device. As noted hereinabove, a 50% duty cycle correction may be accomplished using the phase generator 10 along with appropriate logic circuits (not shown). However, a dedicated DCC that generates 50% duty cycle output(s) may be preferable in certain circuit configurations. The 50% DCC circuit 26 in FIG. 2 is one such dedicated DCC. As shown in FIG. 2, the 50% DCC 26 may be used in conjunction with a DLL 28. The DLL 28 provides synchronization between an external reference clock 30 and a device's internal clock (e.g., a clock that is used to perform various signal processing tasks within an electronic device or a memory chip). The external clock 30 may be typically the external system clock serving the microprocessor (and other system components present in the system along with the electronic device containing the DLL 28) or a delayed/buffered version of it. The system clock 30 may be supplied to the DLL 28 via one or more clock buffers (not shown). The other input to the DLL 28 may be supplied through the feedback loop that includes an I/O delay model 34, which receives the Clock Out 0° signal 19 at one of the outputs of the 50% DCC 26 and provides an appropriately delayed version of the output signal 19 (here, the feedback clock 36) to a phase detector (not shown) in the DLL 28 for phase comparison and clock synchronization. The I/O delay model 34 may function as a buffer or dummy delay circuit so that the output 36 (“the feedback clock”) of the delay model 34 may effectively represent the internal clock that is provided to various circuit elements in the electronic device (e.g., a memory device) (not shown) containing the circuit configuration 25. Thus, the I/O delay model 34 attempts to maintain the phase relationship between the external clock 30 and the signal 36 as close as possible to the phase relationship that exists between the external clock 30 and the electronic device's (e.g., a memory's) internal clock, which, in FIG. 2, is one of the Clock Out 0° 19 or Clock Out 180° 22 signals.
It is noted here that for the sake of simplicity and ease of discussion, signals or circuit elements having similar functionality are referred to herein using identical reference numerals even though these signals or circuit elements may not be physically identical from one configuration to another. Thus, for example, the DLL Clock Out signal is given the same reference numeral “18′” as that given to the Clock In signal in FIG. 1 (and FIG. 3) because both of these signals function as inputs to a DCC (e.g., the phase generator 10 in FIG. 1, and the DCC 26 in FIGS. 2-3). Thus, a clock signal input to a DCC is referenced using the reference numeral “18” irrespective of the shape or duty cycle of the input clock. That is, the Clock In signal 18 in FIG. 1 and the DLL Clock Out signal 18 in FIG. 2 may not have identical shape or duty cycle, even though they have the same reference numeral. Similarly, for ease of discussion, all output clocks (e.g., Clock Out 0° signal 19, Clock Out 180° signal 22, etc.) from a DCC (whether a simple phase generator as in FIG. 1 or a dedicated 50% DCC as in FIGS. 2-3) are referred to herein using the same reference numerals despite the fact that these clocks may not be physically identical. Various common circuit elements (e.g., delay lines, phase detector, etc.) having similar functionality in different embodiments discussed herein are also referred to using identical reference numerals. As noted, the usage of same reference numerals for various DCC circuit elements and input/output clocks is preferred for ease of discussion only. It is further observed here that the additional mention of “50%” may be absent from the usage of the term “DCC” hereinbelow, but, it should be apparent from the context of discussion whether the term “DCC” refers to a “50% DCC” or any other form of DCC (e.g., the phase generator 10).
The DLL 28 may generate two output signals—the DLL Clock Out signal 18 and the DLL Lock Signal 32—both of which may be supplied as inputs to the 50% DCC 26. The DLL Clock Out signal 18 may be a phase synchronized version of the external clock 30, whereas the DLL Lock signal 32 may provide an indication to the DCC 26 when the DLL 28 is “locked” (e.g., when the rising edge of the system clock 30 is coincident with the rising edge of the feedback clock 36). The DLL Lock signal 32 may thus allow the DCC 26 to establish its own “lock” (discussed later hereinbelow). The DCC 26 corrects for any static duty-cycle problem in its input reference clock (i.e., the DLL output clock 18) and generates two output clocks—the Clock Out 0° signal 19, and the Clock Out 180° signal 22 having 0° and 180° phase differences, respectively, from the DCC input clock (i.e., the DLL Clock Out signal 18). Each of these two output clocks 19, 22, has a 50% duty cycle as the name “50% DCC” suggests.
FIG. 3 illustrates a detailed block diagram layout for the 50% DCC unit 26 of FIG. 2. As shown, the configuration of the DCC unit 26 is significantly similar to the phase generator 10 in FIG. 1, except for two changes that result in generation of output clocks with 50% duty cycles from an input clock of any other duty cycle. First, the Clock In signal 18 (input clock to DCC 26 from DLL 28 in FIG. 2) is not directly supplied to the first delay line 12 as in FIG. 1, but through a clock frequency divider unit 38. Thus, the input clock is supplied to the divide-by-2 frequency divider 38 that divides the input clock frequency by two. The output 40 (also designated by circled letter “A”) of this frequency divider 38 is then supplied as an input to the phase detector 16, an input to the first delay line 12, and also as an input to a clock edge detector unit 42. Second, the output clocks 19, 22 are generated through the clock edge detector 42 instead of directly from the input clock 18 and the output from the first delay line 12 as was the case in FIG. 1. Thus, the output 44 (also designated by circled letter “C”) of the first delay line 12 is supplied as a second input of the edge detector unit 42, which performs clock edge detection (here, a logic XOR or “exclusive OR” function) on the two input clocks 40, 44 to generate the 50% duty cycle output clocks 19, 22. The rest of the circuit elements and signals in FIG. 3 are identical to those shown in FIG. 1 and, hence, additional discussion thereof is not provided herein for the sake of brevity. It is, however, noted here that the Clock Out 360° signal 20 at the output of the second delay line 14 is conveniently referenced using a circled letter “B.” Furthermore, only one of the DLL outputs from FIG. 2—the DLL Clock Out signal 18—is shown in FIG. 3 (as the Clock In signal 18), because of lack of relevance of the second output (i.e., the DLL Lock signal 32) with the present discussion. It is evident, however, that such DLL Lock signal 32 may be present as an input to the DCC unit 26 in a real life implementation.
Thus, in the configuration of FIG. 3, the incoming clock frequency is divided by two before the clock enters the delay loop of the DCC 26. Therefore, instead of attempting to lock rising edges of two phase detector input clocks as was the case in the configuration 10 of FIG. 1, the phase detector 16 in FIG. 3 is modified to lock the rising edge of the feedback clock 20 (circled letter “B”) to the falling edge of its reference clock input (i.e., the clock signal 40 or circled letter “A” signal input to the phase detector 16) and vice versa. The intermediate output clocks 40, 44 are multiplied back up to the original frequency using edge detection through the edge detector unit 42 which performs XOR operation on its input clocks 40, 44 to obtain the final 50% duty cycle outputs 19, 22. In FIG. 3, both the rising and falling edges of the clock 40 are used (in phase detector 16, in delay line 12, and in XOR unit 42) to generate the final outputs 19, 22. Therefore, it is assumed that the delay lines 12, 14 preserve proper duty cycle of their respective input clocks so as to allow such dual-edge operation.
FIG. 4 illustrates the operation of the 50% DCC unit 26 in FIG. 3 through a set of waveforms of various clock signals in the 50% DCC unit 26. The signals in FIG. 4 are identified by corresponding reference numerals of various input, intermediate, and output clock signals in FIG. 3. It is shown in FIG. 4 that the phase detector 16 is modified to lock the rising edge of its first input clock 20 to the falling edge of its second input clock 40, and vice versa (i.e., locking the falling edge of clock 20 to the rising edge of clock 40) because of the input clock frequency division at block 38 (which aligns rising edge of one clock to the falling edge of the another of the two clocks 20, 40 as shown in FIG. 4). The Clock Out 360° signal 20 (represented by circled letter “B”) is still 360° out of phase with the input clock 18, but with half the frequency of the input clock 18. The “midpoint” delayed signal—i.e., the intermediate clock 44 (circled letter “C”)—at the output of the first 12 of the two matched delay lines 12, 14 is a delayed version (wherein the delay is determined by the control input 24 from the phase detector 16 as discussed hereinbefore) of the clock 40, but is not exactly 180° out of phase with the input clock 18 as can be seen from FIG. 4. However, the final output signal Clock Out 180° signal 22 is exactly 180° out of phase with the input clock 18, but with 50% duty cycle. Similarly, the other final output signal 19 is exactly in phase (0° phase difference) with the input clock 18, but with its duty cycle corrected to 50%.
It is seen from the waveforms in FIG. 4 that because of frequency division at block 38 (FIG. 3), all internal clock frequencies (of clocks 40, 20, and 44) have been reduced in half, therefore also reducing DCC current consumption by half (resulting in power savings). This frequency reduction, however, allows the DCC 26 to operate at still faster frequencies (of the input clock 18 and, hence, of the external system clock 30 (FIG. 2)) because of the same-speed limitations of the internal circuitry in an electronic device (i.e., all internal circuits within an electronic device should be capable of operating at the same clock speed). As noted before, the output signals 19, 22 are not only in the correct phase (in phase or 180° out of phase, whichever is applicable), but the duty cycle of each output clock 19, 22 is nearly equal to 50%, which is not the case for the output clocks 19, 22 in a non-frequency-divided version of DCC (i.e., the phase generator 10 in FIG. 1). In the non-divided version 10, the phases of output clocks 19, 22 are correct (in phase or 180° out of phase, whichever is applicable) with reference to the input clock 18, but the duty cycle of each output clock 19-20, 22 is the same as the duty cycle of the input clock 18. On the other hand, the duty cycles of the input 18 and output clocks 19, 22 may be different in the DCC circuit 26 in FIG. 3 as can be seen from the relevant waveforms in FIG. 4. The DCC unit 26 is a dedicated 50% DCC because it achieves the desired 50% duty cycle correction in its output clocks 19, 22 without any further processing.
The waveforms in FIG. 4 show the reduced-frequency 50% DCC 26 operating properly after the DCC feedback loop (formed by the clocks 40 and 20) is “locked” (i.e., the rising edge of the feedback clock 20 is locked or synchronized to the falling edge of the reference clock 40, or vice versa). However, at the time of initialization of the DCC 26, the output clocks 19 and 22 are very close in phase (which is determined by the minimum, intrinsic delay for each forward delay line 12 and 14). During this initialization, the XOR or edge detection function in the unit 42 will produce narrow glitches or pulses, or may not produce any output clock signal at all. FIG. 5 shows a set of waveforms of various clock signals in the 50% DCC unit 26 of FIG. 3 at the time of initialization of DCC 26 and before the DCC is “locked” (i.e., before the DCC feedback loop signals 20 and 40 are phase synchronized as noted hereinbefore). The narrow glitches or pulses in the output clocks 19, 22 are evident in their corresponding waveforms in FIG. 5. It is observed here that this problem of narrow glitches only affects the multiplied output (i.e., outputs 19, 22 from the XOR unit 42), but does not affect the fed-back clock signal (i.e., the Clock Out 360° signal 20). Therefore, the DCC 26 will eventually begin to lock (because the phase detector inputs 20, 40 are not affected by the multiplication operation in the XOR unit 42), and the pulses in the final outputs 19, 22 will start getting wider until they are at 50% duty cycle and the DCC loop is locked.
It is seen from FIG. 2 that the DCC 26 is placed after the DLL 28 in the signal propagation path (i.e., DCC 26 is in the forward-path delay of the system). In that situation, to ensure proper/careful initialization of DLL 28 and DCC 26, the following initialization sequence is used: (1) First, the DLL 28 is initialized and locked, and (2) once the DLL is locked and enters the quiescent state (as indicated by the assertion of the DLL Lock Signal 32 in FIG. 2), the DCC 26 is then allowed to lock (based on the status of the DLL Lock signal 32). In this sequential locking mechanism and because DCC 26 is in the forward-path delay of the system, if the clocks are lost because of the narrow pulse width upon DCC initialization (as shown by the narrow pulses in the waveforms for output clocks 19, 22 in FIG. 5), there may be no clock fed back to the DLL 28 because the glitches in the DCC output clock 19, which is fed back to DLL 28 as shown in FIG. 2, may collapse in the DLL feedback path (through the I/O delay model 34 shown in FIG. 2). In that case, the DLL 28 may lose its initial lock or cannot maintain it and, hence, may itself never initialize and may not allow DCC 26 to lock either. Such instability in establishing DLL and DCC locks may consume significant system time (in terms of many, wasted clock cycles of the system clock 30) and power before both of these components are locked, if at all.
It is therefore desirable to devise an initialization scheme for reduced frequency (obtained using input clock frequency division as discussed hereinbefore), 50% DCC that prevents the instability (noted above) in locking the DCC and DLL upon system initialization. It is also desirable that this initialization scheme for the 50% DCC be able to initialize swiftly, and properly lock the DCC (and DLL) without significant power consumption.